View 141540_1115542.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mc141540 1 motorola cmos the mc141540 is a high performance hcmos device designed to interface with a microcontroller unit to allow colored symbols or characters to be displayed on a color monitor. the onchip pll allows both multisystem operation and selfgeneration of system timing. it also minimizes the mcu's burden through its builtin 273 bytes display/control ram. by storing a full screen of data and control information, this device has a capability to carry out `screenrefresh' without mcu supervision. since there is no spacing between characters, special graphicsoriented characters can be generated by combining two or more character blocks. special functions such as character bordering or shadowing, multilevel windows, double height and double width, and programmable vertical length of character can also be incorporated. furthermore, neither massive information update nor extremely high data transmission rate are expected for normal on screen display operation, and serial protocols are implemented in lieu of any parallel formats to achieve minimum pin count. ? fixed resolution: 320 (cga) dots per line ? fully programmable character array of 10 rows by 24 columns ? 273 bytes direct mapping display ram architecture ? internal pll generates a wideranged system clock ? for highend monitor application, maximum horizontal frequency is 100 khz (32 mhz dot clock) ? programmable vertical height of character to meet multisync requirement ? programmable vertical and horizontal positioning for display center ? 128 characters and graphic symbols rom ? 10 x 16 dot matrix character ? characterbycharacter color selection ? a maximum of four selectable colors per row ? double character height and double character width ? character bordering or shadowing ? three fully programmable background windows with overlapping capability ? single positive 5 v supply ? mc141540p4 is a replacement for xc141540p with two symbols added in rom addresses `5c' and `5e' order this document by mc141540/d
semiconductor technical data pin assignment p suffix plastic dip case 648 ordering information mc141540p4 plastic dip 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 fbkg b g r v ss v dd vflb htone v dd(a ) rp vco scl(sck) sda(mosi) ss hflb v ss(a) ? motorola, inc. 1997 rev 1 2/97 tn97031200
mc141540 motorola 2 block diagram ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ???????? ???????? ???????? ???????? ???????? ????? ????? ????? ????? ????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? data receiver bus arbitration vertical control circuit horizontal control background generator color encoder 10bit shift register character roms row buffer logic waddr wcolor ccolors chs cws crs wcolor and control ccolors and select waddr sc hord 5 cclk dhor lp 4 blackedge mclk sda(mosi) rp vco scl(sck) data ra,ca,da rfg addrc y 9 3 8 7 8 6 10 3 2 5 54 11 15 14 13 12 3 w r chs 54 15 13 8 5 26 nrow 15 13 cws shadow fbkg htone b g r char craddr osd_en verd hord rdata luminance bsen shadow bsen osd_en 5 ch 4 and pll and control 8 verd 4 z 26 8 and select 6 10 9 1 16 v dd v ss (a) v dd(a) mclk v ss ???????? ???????? ???????? ???????? ???????? memory and data management ss vflb hflb
mc141540 3 motorola absolute maximum ratings voltage referenced to v ss symbol characteristic value unit v dd supply voltage 0.3 to + 7.0 v v in input voltage v ss 0.3 to v dd + 0.3 v id current drain per pin excluding v dd and v ss 25 ma ta operating temperature range 0 to 85 c t stg storage temperature range 65 to + 150 c note: maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteris- tics tables or pin description section. ac electrical characteristics (v dd = v dd(a) = 5.0 v, v ss = v ss(a) = 0 v, t a = 25 c, voltage referenced to v ss ) symbol characteristic min typ max unit t r t f output signal (r, g, b, fbkg and htone) c load = 30 pf, see figure 1 rise time fall time e e e e 10 10 ns ns f hflb hflb input frequency e e 100 khz dc characteristics v dd = v dd(a) = 5.0 v 10%, v ss = v ss(a) = 0 v, t a = 25 c, voltage referenced to v ss symbol characteristic min typ max unit v oh high level output voltage i out = 5 ma v dd 0.8 e e v v ol low level output voltage i out = 5 ma e e v ss + 0.4 v v il v ih digital input voltage (not including sda and scl) logic low logic high e 0.7 v dd e e 0.3 v dd e v v v il v ih input voltage of pin sda and scl in spi mode logic low logic high e 0.7 v dd e e 0.3 v dd e v v i ii highz leakage current (r, g, b and fbkg) 10 e + 10 m a i ii input current (not including rp, vco, r, g, b, fbkg and htone) 10 e + 10 m a i dd supply current (no load on any output) e 9* e ma * not a guaranteed limit. 90% 10% 90% 10% tf tr figure 1. switching characteristics this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid applica- tions of any voltage higher than the maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open.
mc141540 motorola 4 pin descriptions v ss(a) (pin 1) this pin provides the signal ground to the pll circuitry. analog ground for pll operation is separated from digital ground for optimal performance. vco (pin 2) pin 2 is a control voltage input to regulate an internal oscil- lator frequency. see the application diagram for the applica- tion values used. rp (pin 3) an external rc network is used to bias an internal vco to resonate at the specific dot frequency. the value of the resis- tor for this pin should be adjusted in order to set the pin volt- age to around half v dd . see the application diagram for the application values used. v dd(a) (pin 4) pin 4 is a positive 5 v supply for pll circuitry. analog pow- er for pll is separated from digital power for optimal perfor- mance. hflb (pin 5) this pin inputs a negative polarity horizontal synchronize signal pulse to phase lock an internal system clock gener- ated by the onchip vco circuit. ss (pin 6) this input pin is part of the spi serial interface. an active low signal generated by the master device enables this slave device to accept data. this pin should be pulled high to termi- nate the spi communication. sda (mosi) (pin 7) data and control messages are being transmitted to this chip from a host mcu via this wire, which is configured as a unidirectional data line. (detailed description of these two protocols will be discussed in the spi section). scl (sck) (pin 8) a separate synchronizing clock input from the transmitter is required for either protocol. data is read at the rising edge of each clock signal. v dd (pin 9) this is the power pin for the digital logic of the chip. vflb (pin 10) similar to pin 5, this pin inputs a negative polarity vertical synchronize signal pulse. htone (pin 11) this pin outputs a logic high during windowing except when graphics or characters are being displayed. it is used to lower the external r, g, and b amplifiers' gain to achieve a transparent windowing effect. fbkg (pin 12) this pin outputs a logic high while displaying characters or windows when the fbkgc bit in the frame control register is 0, and output a logic high only while displaying characters when the fbkgc bit is 1. it is defaulted to highimpedance state after poweron, or when there is no output. an external 10 k w resistor pulled low is recommended to avoid level tog- gling caused by hand effect when there is no output. b,g,r (pins 13,14,15) mosd color output is ttl level rgb to the host monitor. these three signals are active high output pins that are in a highimpedance state when mosd is disabled. v ss (pin 16) this is the ground pin for the digital logic of the chip. system description mc141540 is a fullscreen memory architecture. refresh is performed by the builtin circuitry after a screenful of dis- play data has been loaded through the serial bus. only changes to the display data need to be input afterward. serial data, which includes screen mapping address, dis- play information, and control messages, are transmitted via the spi bus. figure 2 contains the spi protocol operating procedure. data is received from the serial port and stored by the memory management circuit. line data is stored in a row buffer for display and refreshing. during this storing and re- trieving cycle, bus arbitration logic patrols the internal traffic to make sure that no crashes occur between the slower seri- al bus receiver and the fast `screenrefresh' circuitry. after the fullscreen display data is received through one of the serial communication interfaces, the link can be terminated if a change of the display is not required. the bottom half of the block diagram contains the hard- ware functions for the entire system. it performs all the mosd functions such as programmable vertical length (from 16 lines to 63 lines), display clock generation (which is phase locked to the incoming horizontal sync signal at pin 5 hflb ), bordering or shadowing, and multiple windowing. communication protocols serial peripheral interface (spi) spi is a threewire serial communication link that requires separate clock (sck) and data (mosi) lines. in addition, an ss slave select pin is controlled by the master transmitter to initiate the receiver. operating procedure to initiate spi transmission, the ss pin is pulled low by the master device to enable mc141540 to accept data. the ss input line must be a logic low prior to the occurrence of sck, and remain low until and after the last (eighth) sck cycle. af- ter all data has been sent, the ss pin is then pulled high by the master to terminate the transmission. no slave address is needed for spi. hence, row and column address informa- tion and display data can be sent immediately after the spi is initiated.
mc141540 5 motorola mosi msb lsb sck last byte first byte figure 2. spi protocol ss data transmission formats after the proper identification by the receiving device, a data train of arbitrary length is transmitted from the master. there are three transmission formats from (a) to (c) as stated below. the data train in each sequence consists of row ad- dress (r), column address (c), and display information (i), as shown in figure 3. in format (a), display information data must be preceded with the corresponding row address and column address. this format is particularly suitable for updat- ing small amounts of data between different rows. however, if the current information byte has the same row address as the one before, format (b) is recommended. ???????????? ???????????? row addr col addr info figure 3. data packet for a fullscreen pattern change that requires a massive information update, or during powerup, most of the row and column addresses of either (a) or (b) formats will be consec- utive. therefore, a more efficient data transmission format (c) should be applied. this sends the ram starting row and col- umn addresses once only, and then treats all subsequent data as display information. the row and column addresses will be automatically incremented internally for each display information data from the starting location. because col- umns 24 through 29 are unused, it is recommended that these locations are filled with dummy data while using format (c) to transmit. the data transmission formats are: (a) r > c > i > r > c > i > . . . . . . . . . (b) r > c > i > c > i > c > i. . . . . . . (c) r > c > i > i > i > . . . . . . . . . . . . . to differentiate the row and column addresses when trans- ferring data from master, the msb (most significant bit) is set, as in figure 4: `1' to represent row, and `0' for column ad- dress. furthermore, to distinguish the column address be- tween formats (a), (b), and (c), the sixth bit of the column address is set to `1' which represents format (c), and `0' for format (a) or (b). however, there is some limitation on using mixed formats during a single transmission. it is permissible to change the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b). ?????????????? ?????????????? ?????????????? ?????????????? address row column column x: don't care d: valid data format bit 0 1 2 3 4 5 6 7 d d d d x x x 1 d d d d d x 0 0 d d d d d x 1 0 a, b a, b, c c figure 4. row & column address bit patterns memory management internal ram is addressed with row and column (coln) numbers in sequence. the spaces between row 0 and coln 0 to row 9 and coln 23 are called display registers, and each contains a character rom address corresponding to a dis- play location on the monitor screen. every data row is associated with two control registers, which are located at coln 30 and 31 of their respective rows, to control the char- acter display format of that row. in addition, three window control registers for each of the three windows, together with three frame control registers, occupy the first 13 columns of row 10. the user should handle the internal ram address location with care, especially those rows with double length alphanu- meric symbols. for example, if row n is destined to be double height on the memory map, the data displayed on screen rows n and n+1 will be represented by the data con- tained in the memory address of row n only. the data of the next row n+1 on the memory map will appear on the screen as n+2 and n+3 row space, and so on. hence, it is not neces- sary to load a row of blank data to compensate for the double row. the user should minimize excessive rows of data in memory in order to avoid overrunning the limited amount of row space on the screen. for rows with double width alphanumeric symbols, only the data contained in the even numbered columns of the memory map are shown. odd numbered columns are treated in the same manner as double height rows. ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? display registers column 29 30 31 0 0 9 row row control registers window 1 window 2 frame crtl reg window 3 10 0 235689 12 23 24... window and frame control registers figure 5. memory map reserved space
mc141540 motorola 6 registers display register ????????????? ????????????? 0 1 2 3 4 5 6 7 ccs0 craddr bit 7 ccs0 e this bit defines a specific character color out of the two preset colors. color 1 is selected if this bit is cleared, and color 2 otherwise. bit 60 craddr e these seven bits address the 128 characters or symbols residing in the character rom. row control registers coln 30 ????????????? ????????????? ????????????? 0 1 2 3 4 5 6 7 cws chs b2 g2 r2 b1 g1 r1 coln 30 bits 72 e color 1 is determined by r1, g1, and b1; color 2 by r2, g2, and b2. bit 1 chs e this bit determines the height of a display symbol. when it is set, the symbol is displayed in double height. bit 0 cws e bit 0 is similar to bit 1; when this bit is set, the character is displayed in double width. coln 31 ?????????????? ?????????????? 0 1 2 3 4 5 6 7 b4 g4 r4 b3 g3 r3 coln 31 bits 72 e color 3 is determined by r3, g3, and b3; color 4 by r4, g4, and b4. window 1 registers row 10 coln 0, 3, or 6 ?????????????? ?????????????? ?????????????? 0 1 2 3 4 5 6 7 row end addr msb lsb row start addr msb lsb coln 0, row 10 3, or 6 row 10 coln 1, 4, or 7 ?????????????? ?????????????? ?????????????? wen ccs1 col start addr msb lsb coln 1, 0 1 2 3 4 5 6 7 row 10 4, or 7 bit 2 wen e this bit enables the background window 1 generation when it is set. bit 1 ccs1 e this additional color select bit provides the characters residing within window 1 with two extra color selections, making a total of four selections for that row. row 10 coln 2, 5, or 8 ???????????? ???????????? rg col end addr msb lsb coln 2, 0 1 2 3 4 5 6 7 b row 10 5, or 8 window 1 occupies columns 02 of row 10; window 2 occupies columns 35; and window 3 occupies columns 68. window 1 has the highest priority, and window 3 the least. if window overlapping occurs, the higher priority win- dow will cover the lower one, and the higher priority color will take over on the overlap window area. if the start address is greater than the end address, this window will not be dis- played. frame control registers coln 9 ???????????? ???????????? 0 1 2 3 4 5 6 7 lsb coln 9 msb vertd bit 70 vertd e these six bits define the vertical starting position. there are a total of 64 steps, with an increment of four horizontal lines per step for each field. the value cannot be zero anytime, and the default value is 4. coln 10 ????????????? ????????????? ????????????? 0 1 2 3 4 5 6 7 lsb coln 10 msb hord bit 60 hord e these bits define the horizontal starting position for character display. five bits give a total of 32 steps and each increment represents a fivedot shift to the right on the monitor screen. the value cannot be zero any- time, and the default value is 5. coln 11 ????????????? ????????????? 7 coln 11 65 4 3 2 1 0 ch5 ch4 ch3 ch2 ch1 ch0 bit 50 ch5ch0 e these six bits determine the dis- played character height. it is possible to have a proper char- acter height by setting a value greater than or equal to 16 on a different horizontal frequency monitor. setting a value be- low 16 will not have a predictable result. figure 6 illustrates how this chip expands the builtin character font to the de- sired height. coln 12 ???????????? ???????????? 7 osd_en coln 12 65 43 21 0 bsen shadow fbkgc bit 7 osd_en e the osd circuit is activated when this bit is set. bit 6 bsen e this bit enables the character bordering or shadowing function when it is set. bit 5 shadow e characters with blackedge shadowing are selected if this bit is set; otherwise bordering prevails. bit 0 fbkgc e bit 0 determines the configuration of the fbkg output pin. when it is clear, the fbkg pin outputs high while displaying characters or windows; otherwise, the fbkg pin outputs high only while displaying characters.
mc141540 7 motorola ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? 16 lines 22 lines 34 lines 25 lines builtin font display character when ch=22 display character when ch=34 when ch=25 display character (10x16 matrix) when ch=16 figure 6. variable character height an ibm pc program called amosd font editoro (rev. 2.0) was written for mc141540 editing purposes. this program generates a set of srecord or binary record for the desired display patterns to be masked onto the character rom of the mc141540. in order to have better character display within windows, it is suggested that the designed character font be placed in the center of the 10 x 16 matrix with equal space on all four sides. the character $00 is predefined for blank characters, and the character $7f is predefined for fullfilled characters. in order to avoid submersion of displayed symbols or char- acters into a background of comparable colors, a feature of bordering which encircles all four sides, or shadowing which encircles only the right and bottom sides of an individual dis- play character, are provided. figure 7 shows how a character is jacketed differently. to make sure that a character is bor- dered or shadowed correctly, at least one blank dot should be reserved on each side of the character font. ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?? ?? ?? ?? ?? ?? ?? ?? ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 bordering ?? ?? ?? ????? ????? ????? ????? ????? ????? ????? ????? ????? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? ? ? ? ? ? ? ? ? ? ? ? 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 shadowing ? ? ? ?? ?? ?? ?? figure 7. character bordering and shadowing frame format and timing figure 8 illustrates the positions of all display characters on the screen relative to the leading edge of horizontal and vertical flyback signals. the shaded area indicates the area outside the asafe viewing areao for the display characters. notice that there are two components in the equations stated in figure 8 for horizontal and vertical delays: fixed delays from the leading edge of hflb and vflb signals, regardless of the values of hord and vertd (47 dots + phase detec- tion pulse width) and one h scan line for horizontal and verti- cal delays, respectively; and variable delays determined by the values of hord and vertd. refer to frame control registers coln 9 and 10 for the definitions of vertd and hord. phase detection pulse width is a function of the external chargeup resistor, which is the 330 k w resistor in a series with 2 k w to vco pin in the application diagram. dot fre- quency is determined by the equation h freq x 320 . for ex- ample, dot frequency is 10.24 mhz if h freq is 32 khz. hence, a dot equals 1/10.24 m s. when double character width is selected for a row, only the evennumbered characters will be displayed, as shown in row 2. notice that the total number of horizontal scan lines in the display frame is variable, depending on the chosen char- acter height of each row. care should be taken while config- uring each row character height so that the last horizontal scan line in the display frame always comes out before the leading edge of vflb of the next frame, to avoid wrapping display characters of the last few rows in the current frame into the next frame. the number of display dots in a horizon- tal scan line is always fixed at 240, regardless of row charac- ter width.
mc141540 motorola 8 ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? vflb hflb 1 row column 2 3 4 5 6 . . . . . . 14 123 0 0 29 28 27 26 double height double width ch50 = 0x21 ch50 = 0x21 & double height standard size 10x16 & double width col 0 col 2 col 4 col 6 col 8 col 10 col 12 col 14 col 28 10x30 dots fixed variable number of h scan lines vertical delay = vertd x 4 + 1 h scan lines horizontal delay = (hord x 5 + 47) dots + phase detection pulse width display frame format ?? ?? area not interfered by display characters ?? ?? display character . . . . . . . . . . . . . . . . hflb figure 8. display frame format figure 9 illustrates the timing of all output signals as a function of window and fastblanking features. line 3 of all three characters is used to illustrate the timing signals. the shaded area depicts the window area. the characters on the left and right appear identical except for the fbkgc bit. the middle character does not have a window as its background. notice that signal htone is active only in the window area. timing of the signal fbkg depends on the configuration of the fbkgc bit. the configuration of the fbkgc bit affects only the fbkg signal timing; it has no effect on the timing of htone. waveform `r, g, or b', which is the actual waveform at r, g, or b pin, is the logical or of waveform `character r, g, or b' and waveform `window r, g, or b'. `character r, g, or b' and `window r, g, or b' are internal signals for illustra- tion purpose only. also notice that htone has exactly the same waveform as `window r, g, or b'. fbkg fbkgc bit = 0 character inside a window character outside a window htone fbkgc bit = 1 character inside a window 3 line 3 window r, g, or b character r, g, or b r, g, or b figure 9. timing of output signals as a function of window and fbkgc bit features font icon combination mc141540 contains 128character rom. the user can create an onscreen menu based on those characters and icons. addresses $00 and $7f are predefined characters. they cannot be modified in any mosds. rom content figures 10 13 show the rom content of mc141540. mask rom is optional for custom parts.
mc141540 9 motorola 00 1b 01 03 02 07 06 05 04 08 09 0a 0b 0f 0e 0d 0c 10 11 12 13 17 1f 16 15 14 1a 19 18 1e 1d 1c figure 10. rom address ($00 $1f) 20 21 23 22 24 25 27 26 28 29 2b 2a 2c 2d 2f 2e 30 31 33 32 34 35 37 36 38 39 3b 3a 3c 3d 3f 3e figure 11. rom address ($20 $3f)
mc141540 motorola 10 40 41 43 42 44 45 47 46 48 49 4b 4a 4c 4d 4f 4e 50 51 53 52 54 55 57 56 58 59 5b 5a 5c 5d 5f 5e figure 12. rom address ($40 $5f) 60 61 63 62 64 65 67 66 68 69 6b 6a 6c 6d 6f 6e 70 71 73 72 74 75 77 76 78 79 7b 7a 7c 7d 7f 7e figure 13. rom address ($60 $7f)
mc141540 11 motorola design considerations distortion motorola's mc141540 has a builtin pll for multisystem application. pin 2 voltage is dcbased for the internal vco in the pll. when the input frequency (hflb) to pin 5 in- creases, the vco frequency will increase accordingly. this forces the pll to a higher locked frequency output. the fre- quency should be equal to 320 x hflb. this is the pixel dot clock. display distortion is caused by noise on pin 2. positive noise increases the vco frequency above normal. the cor- responding scan line will be shorter accordingly. in contrast, negative noise causes the scan line to be longer. the net re- sult will be distortion on the display, especially on the right hand side of the display window. in order to have distortionfree display, the following rec- ommendations should be considered: ? only analog part grounds (pin 2 to pin 4) can be con- nected to pin 1(v ss(a) ). v ss and other grounds should be connected to pcb common ground. the v ss(a) and v ss grounds should be totally separated (i.e. v ss(a) is float- ing). refer to the application diagram for the ground con- nections. ? the dc supply path for pin 9 (v dd ) should be separated from other switching devices. ? the lc filter should be connected between pin 9 and pin 4. refer to the values used in the application diagram. ? biasing and filter networks should be connected to pin 2 and pin 3. refer to the recommended networks in the ap- plication diagram. ? two small capacitors can be connected between pins 2 and 3, and between pins 3 and 4. jittering most display jittering is caused by hflb jittering on pin 5. care must be taken if the hflb signal comes from the fly- back transformer. a short path and shielded cable are rec- ommended for a clean signal. a small capacitor can be added between pin 5 and pin 16 to smooth the signal. refer to the value used in the application diagram. display dancing most display dancing is caused by interference of the seri- al bus. it can be avoided by adding series resistors to the se- rial bus. application diagram mps2369 100 m h 0.1 m f 100 m f analog ground floating 3.3 k 100 100 100 240 240 240 v cc v cc 1 k 1 k 1 k 0.1 m f 10 m f 9 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 0.01 m f 1 k 0.047 m f 33 pf 33 pf 100 100 100 v dd v ss r g b fbkg htone vflb v ss(a) vco rp hflb ss sda(mosi) scl(sck) v dd(a) hflb 2 k vflb htone fbkg b g r 330 k digital ground common ground analog ground digital ground mosd iic(spi) bus 330 pf
mc141540 motorola 12 package dimensions p suffix plastic dip case 64808 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405, denver, colorado 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 internet : http://www.mot.com/sps/ mc141540/d ?

▲Up To Search▲

Price & Availability of 141540

	To Download 141540 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .